There are diodes, Insulated Gate Bipolar Transistors (IGBTs), etc., of a 600V, 1200V, or 1700V withstand voltage class, as power semiconductor devices. Improvements of characteristics of these devices have advanced recently. The power semiconductor devices are used in power conversion systems, such as a high-efficiency power-saving converter-inverter system, and essential for controlling rotation motors and servomotors.
Characteristics of low loss, power saving, high speed, high efficiency, and environmental friendliness, i.e., no bad influence on surroundings are required of such a power controller. For these requirements, there is commonly known a method of thinning the rear surface of a typical semiconductor substrate (e.g. silicon wafer) by grinding or the like after forming the front surface side region of the semiconductor substrate, and then performing ion implantation of an element with a predetermined concentration from the ground surface side, followed by heat treatment. See JP-T-2002-520885, which corresponds to USPGP 2001/005024 (Patent Document 1). Incidentally, the carrier frequencies of these IGBTs are to be extended to not less than 1 to 10 kHz.
A diode having a broad buffer structure has been further proposed. The broad buffer structure is a structure in which the average concentration distribution of an N− drift layer has a peak (local maximum) substantially near the midpoint of the N− drift layer so that the concentration decreases with a gradient toward both anode and cathode sides. See JP-A-2003-318412, which corresponds to USPGP 2004/041225 (Patent Document 2).
The broad buffer structure type diode can achieve soft recovery characteristics and oscillation suppressing effect in a high-speed operation (e.g., carrier frequency: 20 kHz or higher) that could hardly be made by a conventional technique of controlling a lifetime distribution while reducing emitter implantation efficiency. As a method for producing the broad buffer structure type diode, Patent Document 2 discloses a method in which an FZ (float zone) bulk wafer is irradiated with protons (H+) and heat treated to thereby provide hydrogen-related defect complex (HRDC), as donors near a projected range Rp inside the bulk.
Besides Patent Document 2, various methods of forming a high-concentration N+ layer using the phenomenon that HRDC are provided as donors by proton irradiation and heat treatment have been proposed. See WO 2007/055352 (Patent Document 3). Specifically, a method of forming an N-type buffer layer with a predetermined thickness in a predetermined position of an N-type drift layer is commonly known. See JP-A-2003-152198, which corresponds to USPGP 2002/130331. A method of forming an N buffer layer between an N− drift layer and an N+ cathode layer with the N buffer layer higher in impurity concentration than the N− drift layer and lower in impurity concentration than the N+ cathode layer and thicker than the N+ cathode layer is also commonly known. See JP-A-2007-158320, which corresponds to USPGP 2007/108558).
There has been further proposed a method in which defects are formed in a silicon wafer by irradiation with ions of a low-mass element on the periodic table, such as protons or helium ions, and the remaining defects are adjusted by heat treatment to thereby reduce lifetime locally. See Power Device & Power IC Handbook, edited by the Institute of Electrical Engineers of Japan, High Performance and High Function Power Device and Power IC Investigation and Research Committee, first edition, pp. 68-71, CORONA Publishing Co., Ltd., Jul. 30, 1996.
When a diode is switched from an ON state to an OFF state (at the time of reverse recovery), a space charge region is spread in an N− drift layer from an anode side toward a cathode side. On this occasion, carriers stored in the drift layer (hereinafter referred to as “stored carriers”) are swept out by the spreading of the space charge region, so that the carrier concentration of the drift layer decreases rapidly. If the spreading of the space charge region per unit voltage is too wide, a larger part of the stored carriers are swept out so that the stored carriers in the drift layer are exhausted in the middle of reverse recovery. Consequently, so-called snappy reverse recovery (hard recovery) occurs so that both reverse recovery voltage and current can produce undesirable oscillated waveforms.
As disclosed in Patent Document 2, in the broad buffer diode according to the related art, the spreading of the space charge region is suppressed by the pinning effect of the space charge region (i.e., the phenomenon that expansion of the depletion layer is stopped at the buffer layer) to prevent the stored carriers from being exhausted to thereby suppress oscillation of both reverse recovery voltage and current. In addition, both conduction loss and reverse recovery loss can be reduced because the thickness of the N− layer can be reduced while the withstand voltage is kept high.
However, reduction of the reverse recovery current value at the time of reverse recovery and reduction of the current decreasing rate until the reverse recovery current's reaching zero as well as suppression of oscillation are required of the diode. This is because reduction of the reverse recovery current to a small value brings an effect on reducing the peak current at the turn-on of a counter arm IGBT to thereby reduce turn-on loss. This is further because reduction of the current decreasing rate at the time of reverse recovery brings an effect on reducing the surge voltage of the diode caused by the stray inductance of the electric circuit.
Although suppression of the surge voltage in the broad buffer structure type diode has been disclosed in the related art documents, there is no description about reducing the reverse recovery current. Adjustment of the carrier concentration of other portions than the broad buffer structure is therefore required for reducing the reverse recovery current. Specifically, there is a problem awaiting solution that implantation of a low concentration of minority carriers into an anode layer as a surface layer of the wafer or lifetime control of the minority carriers must be performed.
Moreover, the lifetime distribution after proton irradiation becomes a distribution in which the lifetime value is locally minimized near the projected range Rp. This reason is that the density of lattice defects is maximized near the projected range Rp in which protons are most localized. The leakage current value JR when the PiN diode having such a lifetime distribution is reverse biased is given by the following expression (1).
                                          J            R                    =                                                    q                (                                                                                                    D                        p                                                                    τ                        p                                                                              +                                                                                    D                        n                                                                    τ                        n                                                                                            )                            ⁢                                                n                  i                  2                                                  N                  D                                                      +                                                            qn                  i                                ⁢                W                                            τ                e                                                    ,                            (        1        )            where q is the elementary electric charge, Dp is the diffusion coefficient of holes, Dn is the diffusion coefficient of electrons, τp is the lifetime of holes, τn is the lifetime of electrons, ni is the carrier concentration of an impurity-free intrinsic semiconductor (i.e., the intrinsic carrier concentration), W is the width of a depletion layer spread in the diode, and τe is the effective lifetime in the depletion layer.
When the diffusion current is sufficiently small, only the current produced in the depletion layer as represented by the second term of the above expression (1) substantially contributes to the leakage current value JR. Accordingly, the maximum of the leakage current value JR is decided by the minimum τmin of the effective lifetime τe in the depletion layer. In a broad buffer structure type diode formed by proton irradiation and heat treatment (annealing) in the related art method, the leakage current value becomes large because, for example, τmin is about 30 ns, which is shorter than τmin of about 600 ns in a broad buffer structure type diode formed by electron beam irradiation applied to an epitaxial wafer. As a result, in the diode formed by proton irradiation in the related art method, the leakage current can produce kinked waveforms that can cause heat runaway of the device.
Accordingly there remains a need to suppress the kinked waveforms in a semiconductor device having soft recovery characteristics in addition to high speed and low-loss characteristics. The present invention addresses this need.